1. Field of the Invention
The present invention relates generally to integrated circuits and more particularly to methods of digitally adjusting capacitance of a node of an integrated circuit.
2. Description of the Related Art
Many integrated circuits are being developed to carry and process very high frequency signals. To handle external signal noise, it is often desirable to match capacitance for a given circuit node. A conventional approach to adjust capacitance is to combine a transistor connected to a series of fixed capacitors to the node. When the transistor is activated, the fixed capacitors are added, thereby adjusting the effective capacitance of the node. An example of this type of system is described in “Digital Systems Engineering”, by Dally and Poulton, pages 590-591, (1998). But, at very high frequencies, the fixed capacitor elements become ineffective in providing capacitance because the RC time constant of the transistor impedance and the fixed capacitor elements is too large compared to the very high frequency signal. Further, it would be desirable if the adjustable capacitance could be selected digitally to provide convenient control.
Accordingly, there is a need for an improved integrated circuit and method of digitally selecting an adjustable capacitance of a node of an integrated circuit, especially with respect to high frequency signals.